High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip
Wang, Zheng, Chattopadhyay, Anupam
Produktnummer:
184fe6c084daf74ebdad6e3787bfbab3a3
| Autor: | Chattopadhyay, Anupam Wang, Zheng |
|---|---|
| Themengebiete: | Architectural Fault Tolerance Architectural Reliability Estimation Asymmetric Reliability Node Fault Tolerance (NFT) Probabilistic Error Masking Matrix (PeMM) Processor Design Reliability Task Mapping Statistical Error Confinement System-Level Design System- Level Reliability Exploration |
| Veröffentlichungsdatum: | 05.07.2017 |
| EAN: | 9789811010729 |
| Sprache: | Englisch |
| Seitenzahl: | 197 |
| Produktart: | Gebunden |
| Verlag: | Springer Singapore |
Produktinformationen "High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip"
This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.
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