High-frequency benchmark circuits for compact model verification with special emphasis on evaluating the impact of physical effects on circuit performance

Accurate compact models for active and passive devices are an integral part of analog high frequency (HF) circuit design. This not only helps to reduce the risk of design errors and increases the chance of “first-pass” working mixed-signal and stand-alone HF circuits but also enables a deeper understanding of circuit operation. While in the last two decades sophisticated (standard) HBT compact models have been developed and made available in commercial simulators, over time the fields of device modeling and analog circuit design have grown apart, as they require very quite different knowledge and skill sets. As a result, the focus of compact model development may not always meet the need of circuit design. On the other hand, the difficulties of circuit designers in understanding the compact models, results in their improper use outside of their validity range or in designs with far too large safety margins since. This leads to the idea of (preferably automated) benchmark circuit design for enenbling compact model verification on the circuit level thus for bridging the above mentioned gap. This thesis focuses on designing benchmark circuits in a step by step procedure targeting compact model verification and technology characterization. Special emphasis is placed on evaluating on how physical effects occurring on the device level impact the circuit behaviour. This has been accomplished by employing the physics-based compact bipolar transistor model HICUM, including various distributed physical effects such as substrate and thermal coupling. For In this thesis, the design of different mm-wave benchmark circuits is presented: power amplifiers, broad-band amplifiers , narrow-band , and wide-band low noise amplifiers . Power amplifiers consisting of power cells with a single or multiple transistors are optimized for performance and are considered for large-signal model verification in extreme operating regions. Furthermore, based on a derived algorithmic approach, two variants of broad-band amplifiers as well as a wide-band low-noise amplifier have been designed, optimized and implemented in an advanced 130nm BiCMOS process. On-wafer small signal and noise measurements have shown quite satisfactory agreement between circuit simulation and measurement. The idea of algorithmic benchmark circuit design has further been extended to benchmark circuits for different SiGe HBT technology nodes defined by the “International Technology Roadmap for Semiconductors (ITRS)”.